32-bit ARM9 Microprocessors
N3290 MJPEG Series The series of specialized, low voltage microprocessors based on ARM926EJ-S core, with rich peripherals and interfaces, equipped with 2D graphics accelerator, MJPEG video codec and Sound Processing Unit. They are designed for multimedia applications.
* Status: P - mass production, S - samples, UD - under development, N - not recommended for new design.
Chip |
Description |
SRAM | SDRAM | Supply voltage [V] | Clock frequency | Operating temperature [°C] | Package | Status * | N32901R1DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- external crystal oscillator
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 34 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, I2C, I2S, USB 1.1 Host and USB 2.0 HS Device, SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, CMOS image sensor interface (compliant with CCIR601 / CCIR656)
- 2-channel 16-bit PWM
| 8 KB | 1M x 16 bit SDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz | -20 – +85 | LQFP-64 (MCP) | P | | N32901U1DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- 2 external crystal oscillators
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 64 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- RTC
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, I2C, I2S, USB 1.1 Host and USB 2.0 HS Device, 3 x SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, JTAG, CMOS image sensor interface (compliant with CCIR601 / CCIR656), 4-wire touch panel
- 4-channel 16-bit PWM
| 8 KB | 1M x 16 bit SDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz & 32.768 kHz | -20 – +85 | LQFP-128 (MCP) | P | | N32901U2DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- 2 external crystal oscillators
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 59 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- RTC
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- TV output
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution: D1 (720X480) for TV output and 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, USB 1.1 Host and USB 2.0 HS Device, 2 x SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, JTAG, CMOS image sensor interface (compliant with CCIR601 / CCIR656), 4-wire touch panel
- 4-channel 16-bit PWM
| 8 KB | 1M x 16 bit SDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz & 32.768 kHz | -20 – +85 | LQFP-128 (MCP) | P | | N329031R1DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- external crystal oscillator
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 34 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, I2C, I2S, USB 1.1 Host and USB 2.0 HS Device, SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, CMOS image sensor interface (compliant with CCIR601 / CCIR656)
- 2-channel 16-bit PWM
| 8 KB | 4M x 16 bit DDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz | -20 – +85 | LQFP-64 (MCP) | P | | N32903U1DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- 2 external crystal oscillators
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 64 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- RTC
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, I2C, I2S, USB 1.1 Host and USB 2.0 HS Device, 3 x SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, JTAG, CMOS image sensor interface (compliant with CCIR601 / CCIR656), 4-wire touch panel
- 4-channel 16-bit PWM
| 8 KB | 4M x 16 bit DDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz & 32.768 kHz | -20 – +85 | LQFP-128 (MCP) | P | | N32903U2DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- 2 external crystal oscillators
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 59 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- RTC
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution 1024x768 for TFT LCD panel
- Sound Processing Unit
- TV output
- interfaces: 2 x UART, 2 x SPI, USB 1.1 Host and USB 2.0 HS Device, 2 x SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, JTAG, CMOS image sensor interface (compliant with CCIR601 / CCIR656), 4-wire touch panel
- 4-channel 16-bit PWM
| 8 KB | 4M x 16 bit DDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz & 32.768 kHz | -20 – +85 | LQFP-128 (MCP) | P | | N32905U1DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- 2 external crystal oscillators
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 64 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- RTC
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, I2C, I2S, USB 1.1 Host and USB 2.0 HS Device, 3 x SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, JTAG, CMOS image sensor interface (compliant with CCIR601 / CCIR656), 4-wire touch panel
- 4-channel 16-bit PWM
| 8 KB | 16M x 16 bit DDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz & 32.768 kHz | -20 – +85 | LQFP-128 (MCP) | P | | N32905U2DN (1650 KB) - ARM926EJ-S core
- operating frequency up to 200 MHz
- 2 external crystal oscillators
- PLL controller (the source of system clock up to 200 MHz)
- multi-chip package (MCP), SDRAM is stacked inside the MCP
- system booting modes: SD card, NAND Flash and SPI Flash memories, USB
- 8 KB I-cache and 8 KB D-cache
- 5-ch DMA controller
- up to 59 GPIOs
- two 32-bit timers
- 24-bit Watchdog
- RTC
- 32 interrupts
- 2D BitBLT graphics accelerator
- 3-ch 10-bit SAR ADC
- 10-bit ADC for MIC input
- 16-bit stereo DAC
- TV output
- JPEG codec
- MJPEG video codec (VGA@30 fps); max. resolution: D1 (720X480) for TV output and 1024x768 for TFT LCD panel
- Sound Processing Unit
- interfaces: 2 x UART, 2 x SPI, USB 1.1 Host and USB 2.0 HS Device, 2 x SD/SDIO/SDHC/MMC/MicroSD and NAND Flash memories, JTAG, CMOS image sensor interface (compliant with CCIR601 / CCIR656), 4-wire touch panel
- 4-channel 16-bit PWM
| 8 KB | 16M x 16 bit DDR | Core: 1.8V ±10%
I/O: 3.3V ±10% | Ext. crystal: 27 MHz / 12 MHz & 32.768 kHz | -20 – +85 | LQFP-128 (MCP) | P | |
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